1. Technical Field
The present invention relates in general to electrical circuitry, and more particularly, to the compensation of field effect on polycrystalline resistors.
2. Description of the Related Art
It is well known in the art of analog integrated circuitry that the resistance of polycrystalline silicon (also referred to as polysilicon, poly-Si or simply poly) varies with the applied voltage in a non-linear fashion in the presence of an electric field. This non-linearity is caused by an accumulation of carriers (and thus reduced resistance) in the presence of a positive electric field, or conversely, by a depletion of carriers (and thus increased resistance) in the presence of a negative electric field. Additional information regarding the non-linearity of polycrystalline silicon resistors can be found, for example, in Sze, S. M., Physics of Semiconductor Devices, 2nd Ed., pp. 362-366.
Because such non-linearity is undesirable in many applications, some conventional analog integrated circuits include features intended to reduce the non-linearity of polycrystalline resistors. FIG. 1A is a section view of a first prior art analog integrated circuit 100 that partially compensates for the non-linearity of a polycrystalline resistor. As shown, analog integrated circuit 100 includes a substrate well 102 coupled to ground, a polycrystalline resistor 106 over substrate well 102, and a metallization layer 110 over polycrystalline resistor 106 that is coupled to Vdd. A first oxide layer 104 is interposed between substrate well 102 and polycrystalline resistor 106, and a second oxide layer 108 is interposed between polycrystalline resistor 106 and metallization layer 110. As is well known to those skilled in the art, oxide layers 104, 108 are dielectric layers that electrically isolate polycrystalline resistor 106 from metallization layer 110 and substrate well 102.
Because metallization layer 110 and substrate well 102 are coupled to different potentials and accordingly have an electric field there between, the non-linearity of polycrystalline resistor 106 is reduced by partial cancellation of the field effect on polycrystalline resistor 106. However, in practice, cancellation of the field effect in analog integrated circuit 100 is only partially successful because of asymmetry in the signal between Vdd and ground and differences in the thicknesses of oxide layers 104, 108 militated by other aspects of the design. In addition, circuit layout considerations often make it difficult to overlay each polycrystalline resistor 106 with a metallization layer 110.
FIG. 1B is a top plan view of a second prior art analog integrated circuit 120 that substantially cancels the field effect on a polycrystalline resistor by employing a “bootstrapped” resistor design. Analog integrated circuit 120 includes one or more series-connected polycrystalline segments 122a-122c, which are each connected in parallel with a respective one of underlying well resistor(s) 124a-124c. Well resistors 124a-124c are characterized by a well width W and a well-to-well distance D.
Although the bootstrapped resistor design employed in the embodiment of FIG. 1B can be effective in avoiding non-linear variations in resistivity to a first order approximation, both the well width W and well-to-well distance D are typically large, meaning that the use of bootstrapped resistors is inefficient in terms of die area (and therefore cost). Additional die area and power may also be consumed by a buffer required to drive the well resistors.